Re: [PATCH 1/5] spi: img-spfi: Limit bit clock to 1/4th of input clock
On Mon, Apr 06, 2015 at 02:29:03PM -0700, Andrew Bresticker wrote: > Although the SPFI BITCLK divider supports a value of up to 255, only > values up to 128 are usable. This results in a maximum possible bit > clock rate of 1/4th the input clock rate.