Messages in this thread | | | Date | Sun, 05 Apr 2015 22:09:27 +0200 | From | Richard Weinberger <> | Subject | Re: [PATCH V2] UBI: power cut emulation for testing |
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Am 05.04.2015 um 22:04 schrieb Pavel Machek: > On Sun 2015-04-05 21:49:27, Richard Weinberger wrote: >> On Sun, Apr 5, 2015 at 9:31 PM, Pavel Machek <pavel@ucw.cz> wrote: >>> On Thu 2015-03-26 23:59:50, david.oberhollenzer@sigma-star.at wrote: >>>> Emulate random power cuts by switching device to ro after a number of >>>> writes to allow simple power cut testing with nand-sim. >>>> >>>> Maximum and minimum number of successful writes before power cut and >>>> what kind of writes (EC header, VID header or none) to interrupt >>>> configurable via debugfs. >>>> >>>> Signed-off-by: David Oberhollenzer <david.oberhollenzer@sigma-star.at> >>>> --- >>>> V2: Remove broken check to prevent multiple triggering >>> >>> Does NAND always finish write of full block during powerfail? >> >> Not sure if I correctly understand your question. >> Unless you don't have special hardware a write can be interrupted and >> can cause problems. > > But this only emulates fail after a full block written, no?
Emulating all aspects of real hardware is almost impossible.
Thanks, //richard
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