Messages in this thread | | | Date | Mon, 27 Apr 2015 20:53:44 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86_64, asm: Work around AMD SYSRET SS descriptor attribute issue |
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On Mon, Apr 27, 2015 at 11:47:30AM -0700, Linus Torvalds wrote: > On Mon, Apr 27, 2015 at 11:38 AM, Borislav Petkov <bp@alien8.de> wrote: > > > > So our current NOP-infrastructure does ASM_NOP_MAX NOPs of 8 bytes so > > without more invasive changes, our longest NOPs are 8 byte long and then > > we have to repeat. > > Btw (and I'm too lazy to check) do we take alignment into account? > > Because if you have to split, and use multiple nops, it is *probably* > a good idea to try to avoid 16-byte boundaries, since that's can be > the I$ fetch granularity from L1 (although I guess 32B is getting more > common).
Yeah, on F16h you have 32B fetch but the paths later in the machine gets narrower, so to speak.
> So the exact split might depend on the alignment of the nop replacement..
Yeah, no. Our add_nops() is trivial:
/* Use this to add nops to a buffer, then text_poke the whole buffer. */ static void __init_or_module add_nops(void *insns, unsigned int len) { while (len > 0) { unsigned int noplen = len; if (noplen > ASM_NOP_MAX) noplen = ASM_NOP_MAX; memcpy(insns, ideal_nops[noplen], noplen); insns += noplen; len -= noplen; } }
> Can we perhaps get rid of the distinction entirely, and just use one > set of 64-bit nops for both Intel/AMD?
I *think* hpa would have an opinion here. I'm judging by looking at comments like this one in the code:
/* * Due to a decoder implementation quirk, some * specific Intel CPUs actually perform better with * the "k8_nops" than with the SDM-recommended NOPs. */
which is a fun one in itself. :-)
-- Regards/Gruss, Boris.
ECO tip #101: Trim your mails when you reply. --
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