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    Subject[tip:perf/core] perf/x86/intel: Limit to half counters when the HT workaround is enabled, to avoid exclusive mode starvation
    Commit-ID:  c02cdbf60b51b8d98a49185535f5d527a2965142
    Gitweb: http://git.kernel.org/tip/c02cdbf60b51b8d98a49185535f5d527a2965142
    Author: Stephane Eranian <eranian@google.com>
    AuthorDate: Mon, 17 Nov 2014 20:07:02 +0100
    Committer: Ingo Molnar <mingo@kernel.org>
    CommitDate: Thu, 2 Apr 2015 17:33:14 +0200

    perf/x86/intel: Limit to half counters when the HT workaround is enabled, to avoid exclusive mode starvation

    This patch limits the number of counters available to each CPU when
    the HT bug workaround is enabled.

    This is necessary to avoid situation of counter starvation. Such can
    arise from configuration where one HT thread, HT0, is using all 4 counters
    with corrupting events which require exclusion the the sibling HT, HT1.

    In such case, HT1 would not be able to schedule any event until HT0
    is done. To mitigate this problem, this patch artificially limits
    the number of counters to 2.

    That way, we can gurantee that at least 2 counters are not in exclusive
    mode and therefore allow the sibling thread to schedule events of the
    same type (system vs. per-thread). The 2 counters are not determined
    in advance. We simply set the limit to two events per HT.

    This helps mitigate starvation in case of events with specific counter
    constraints such a PREC_DIST.

    Note that this does not elimintate the starvation is all cases. But
    it is better than not having it.

    (Solution suggested by Peter Zjilstra.)

    Signed-off-by: Stephane Eranian <eranian@google.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: bp@alien8.de
    Cc: jolsa@redhat.com
    Cc: kan.liang@intel.com
    Cc: maria.n.dimakopoulou@gmail.com
    Link: http://lkml.kernel.org/r/1416251225-17721-11-git-send-email-eranian@google.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    ---
    arch/x86/kernel/cpu/perf_event.h | 2 ++
    arch/x86/kernel/cpu/perf_event_intel.c | 22 ++++++++++++++++++++--
    2 files changed, 22 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
    index 2ba71ec..176749c 100644
    --- a/arch/x86/kernel/cpu/perf_event.h
    +++ b/arch/x86/kernel/cpu/perf_event.h
    @@ -134,6 +134,8 @@ enum intel_excl_state_type {
    struct intel_excl_states {
    enum intel_excl_state_type init_state[X86_PMC_IDX_MAX];
    enum intel_excl_state_type state[X86_PMC_IDX_MAX];
    + int num_alloc_cntrs;/* #counters allocated */
    + int max_alloc_cntrs;/* max #counters allowed */
    bool sched_started; /* true if scheduling has started */
    };

    diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
    index 4773ae0..4187d3f 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel.c
    @@ -1897,7 +1897,7 @@ intel_start_scheduling(struct cpu_hw_events *cpuc)
    xl = &excl_cntrs->states[tid];

    xl->sched_started = true;
    -
    + xl->num_alloc_cntrs = 0;
    /*
    * lock shared state until we are done scheduling
    * in stop_event_scheduling()
    @@ -1963,7 +1963,6 @@ intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
    */
    if (cpuc->is_fake)
    return c;
    -
    /*
    * event requires exclusive counter access
    * across HT threads
    @@ -1977,6 +1976,18 @@ intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
    xl = &excl_cntrs->states[tid];
    xlo = &excl_cntrs->states[o_tid];

    + /*
    + * do not allow scheduling of more than max_alloc_cntrs
    + * which is set to half the available generic counters.
    + * this helps avoid counter starvation of sibling thread
    + * by ensuring at most half the counters cannot be in
    + * exclusive mode. There is not designated counters for the
    + * limits. Any N/2 counters can be used. This helps with
    + * events with specifix counter constraints
    + */
    + if (xl->num_alloc_cntrs++ == xl->max_alloc_cntrs)
    + return &emptyconstraint;
    +
    cx = c;

    /*
    @@ -2624,6 +2635,8 @@ static void intel_pmu_cpu_starting(int cpu)
    cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];

    if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
    + int h = x86_pmu.num_counters >> 1;
    +
    for_each_cpu(i, topology_thread_cpumask(cpu)) {
    struct intel_excl_cntrs *c;

    @@ -2637,6 +2650,11 @@ static void intel_pmu_cpu_starting(int cpu)
    }
    cpuc->excl_cntrs->core_id = core_id;
    cpuc->excl_cntrs->refcnt++;
    + /*
    + * set hard limit to half the number of generic counters
    + */
    + cpuc->excl_cntrs->states[0].max_alloc_cntrs = h;
    + cpuc->excl_cntrs->states[1].max_alloc_cntrs = h;
    }
    }


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