Messages in this thread Patch in this message | | | From | Tomeu Vizoso <> | Subject | [PATCH v6 02/15] of: Document long-ram-code property in nvidia,tegra20-apbmisc | Date | Thu, 12 Feb 2015 15:06:18 +0100 |
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Needed to properly decode the ram code register.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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v3: * Clarify wording as suggested by Mikko --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index 47b205c..4556359 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -10,3 +10,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit). -- 1.9.3
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