Messages in this thread | | | Date | Thu, 10 Dec 2015 00:37:27 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing |
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On Wed, Dec 09, 2015 at 03:22:29PM -0800, Harish Chegondi wrote:
> On 12/08/2015 12:37 AM, Peter Zijlstra wrote: > > On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote: > >> Knights Landing core is based on Silvermont core with several differences. > >> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the > >> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs > > > >> +/* Knights Landing */ > >> +void intel_pmu_lbr_init_knl(void) > >> +{ > >> + x86_pmu.lbr_nr = 8; > >> + x86_pmu.lbr_tos = MSR_LBR_TOS; > >> + x86_pmu.lbr_from = MSR_LBR_NHM_FROM; > >> + x86_pmu.lbr_to = MSR_LBR_NHM_TO; > >> + > >> + x86_pmu.lbr_sel_mask = LBR_SEL_MASK; > >> + x86_pmu.lbr_sel_map = snb_lbr_sel_map;
> > Also, unlike Silvermont, this thing seems to have hardware LBR filters. > > So would it not be more accurate to say the KNL has a big core LBR > > instead? (Note that this LBR setup isn't specific to Xeon's, all of the > > Core chips have this, including the client parts).
> We cannot say that KNL has a big core LBR. This is because > architectural MSR IA32_PERF_CAPABILITIES[5:0] which indicates the > format of the address that is stored in the LBR stack is different for > KNL (IA32_PERF_CAPABILITIES[5:0] = 0x1) and big core (for example, > Haswell IA32_PERF_CAPABILITIES[5:0]=0x4). Haswell LBR stack has TSX > info which KNL LBR stack doesn't have.
Fair enough I suppose. Applied the patch.
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