Messages in this thread | | | Date | Mon, 9 Nov 2015 23:02:32 +0100 | From | Peter Zijlstra <> | Subject | Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error |
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On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@ni.com wrote:
> The Intel Xeon E5 processor family suffers from errata[1] BT81:
> +#ifdef CONFIG_X86_TSC > + /* > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. > + * The TSC registers for CPUs other than CPU0 are not cleared by a warm > + * reset resulting in a constant offset error. > + */ > + if ((c->x86 == 6) && (c->x86_model == 0x3f)) > + set_cpu_bug(c, X86_BUG_TSC_OFFSET); > +#endif
That's hardly a family, that's just one, Haswell server.
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