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SubjectRe: [PATCH 0/2] "big hammer" for DAX msync/fsync correctness
On Wed, Oct 28, 2015 at 06:24:29PM -0400, Jeff Moyer wrote:
> Ross Zwisler <ross.zwisler@linux.intel.com> writes:
>
> > This series implements the very slow but correct handling for
> > blkdev_issue_flush() with DAX mappings, as discussed here:
> >
> > https://lkml.org/lkml/2015/10/26/116
> >
> > I don't think that we can actually do the
> >
> > on_each_cpu(sync_cache, ...);
> >
> > ...where sync_cache is something like:
> >
> > cache_disable();
> > wbinvd();
> > pcommit();
> > cache_enable();
> >
> > solution as proposed by Dan because WBINVD + PCOMMIT doesn't guarantee that
> > your writes actually make it durably onto the DIMMs. I believe you really do
> > need to loop through the cache lines, flush them with CLWB, then fence and
> > PCOMMIT.
>
> *blink*
> *blink*
>
> So much for not violating the principal of least surprise. I suppose
> you've asked the hardware folks, and they've sent you down this path?

Sadly, yes, this was the guidance from the hardware folks.


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