Messages in this thread | ![/](/images/icornerl.gif) | | Date | Thu, 22 Oct 2015 10:29:59 +0200 | From | Jean-Francois Moine <> | Subject | Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI |
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On Thu, 22 Oct 2015 10:05:08 +0200 Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> > + uart0: serial@01c28000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0x01c28000 0x400>; > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > + reg-shift = <2>; > > + reg-io-width = <4>; > > + clocks = <&bus_gates 112>; > > + resets = <&bus_rst 208>; > > It's a bit weird that the clocks and reset indices don't match, > usually they do. > > What's even weirder is that there's a 96 offset between the two (4 * > 32), is this expected?
Yes, this is conform to the H3 documentation.
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