Messages in this thread | | | Date | Wed, 21 Oct 2015 15:44:52 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 5/5] x86, perf: Avoid context switching LBR_INFO when not needed |
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On Tue, Oct 20, 2015 at 11:46:37AM -0700, Andi Kleen wrote: > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -2844,7 +2844,7 @@ static void intel_pmu_cpu_starting(int cpu) > /* > * Deal with CPUs that don't clear their LBRs on power-up. > */ > - intel_pmu_lbr_reset(); > + intel_pmu_lbr_reset(1);
s/1/true/ ?
> @@ -242,7 +245,7 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx) > > if (task_ctx->lbr_callstack_users == 0 || > task_ctx->lbr_stack_state == LBR_NONE) { > - intel_pmu_lbr_reset(); > + intel_pmu_lbr_reset(task_ctx->need_info > 0); > return; > } > > @@ -317,7 +320,7 @@ void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) > * stack with branch from multiple tasks. > */ > if (sched_in) { > - intel_pmu_lbr_reset(); > + intel_pmu_lbr_reset(!task_ctx || task_ctx->need_info > 0); > cpuc->lbr_context = ctx; > } > } > @@ -340,7 +343,7 @@ void intel_pmu_lbr_enable(struct perf_event *event) > * avoid data leaks. > */ > if (event->ctx->task && cpuc->lbr_context != event->ctx) { > - intel_pmu_lbr_reset(); > + intel_pmu_lbr_reset(!(event->hw.branch_reg.reg & LBR_NO_INFO)); > cpuc->lbr_context = event->ctx; > } > cpuc->br_sel = event->hw.branch_reg.reg;
Are you sure none of that will result in some data leak in a weird corner case?
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