Messages in this thread | | | From | Vineet Gupta <> | Subject | Re: [RFC] perf: fix building for ARCv1 | Date | Mon, 19 Oct 2015 09:46:35 +0000 |
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On Monday 19 October 2015 03:05 PM, Peter Zijlstra wrote: > On Mon, Oct 19, 2015 at 09:28:43AM +0000, Vineet Gupta wrote: >> > On Monday 19 October 2015 11:20 AM, Andi Kleen wrote: >>> > > Vineet Gupta <Vineet.Gupta1@synopsys.com> writes: >>>> > >> But this user space - so IMHO UP/SMP doesn't matter and we can't simulate them in >>>> > >> C just by itself. >>> > > It matters when you access the perf ring buffer which is updated by kernel. >> > >> > That's part of the problem. The issue is with atomic_* APIs proliferation in perf >> > user space code which assumes native atomix r-m-w support which is not always >> > true. So I think we still need a feature detection mechanism and if absent leave >> > the ball in arch court by calling arch_atomic_* which can use creative or half >> > working measures so perf will work to some extent atleast and not bomb outright. >> > >> > Also can u please elaborate a bit on "simulate them in C" - u mean just simple >> > unprotected LD, OP, ST or do u fancy usage of futex etc? > Doesn't ARMv5 have a cmpxchg syscall to deal with this? It does an > IRQ-disabled load-op-store sequence.
Yeah I remember seeing some syscall like that in ARM.
On ARC we could use the atomic EXchange to implement a user space only binary semaphore - these atomic ops will be small duration so it is OK to spin wait for a little bit. That's how the old pthread library worked for ARC w/o any atomic support.
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