Messages in this thread | | | Date | Thu, 1 Oct 2015 13:01:19 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [PATCH 01/25] x86, fpu: add placeholder for Processor Trace XSAVE state |
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On Mon, 28 Sep 2015, Dave Hansen wrote: > From: Dave Hansen <dave.hansen@linux.intel.com> > > There is an XSAVE state component for Intel Processor Trace. But, > we do not use it and do not expect to ever use it. > > We add a placeholder in the code for it so it is not a mystery and > also so we do not need an explicit enum initialization for Protection > Keys in a moment. > > Why will we never use it? According to Andi Kleen: > > The XSAVE support assumes that there is a single buffer > for each thread. But perf generally doesn't work this > way, it usually has only a single perf event per CPU per > user, and when tracing multiple threads on that CPU it > inherits perf event buffers between different threads. So > XSAVE per thread cannot handle this inheritance case > directly. > > Using multiple XSAVE areas (another one per perf event) > would defeat some of the state caching that the CPUs do. > > Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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