Messages in this thread | | | Date | Wed, 14 Jan 2015 18:04:08 +0100 | From | Radim Krčmář <> | Subject | Re: [PATCH] KVM: x86: amend APIC lowest priority arbitration |
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2015-01-09 15:37+0100, Radim Krčmář: > Lowest priority should take the task priority into account. > > SDM 10.6.2.4 Lowest Priority Delivery Mode. > (Too long to quote; second and last paragraphs are relevant.) > > Before this patch, we strived to have the same amount of handled > lowest-priority interrupts on all VCPUs. > This is only a complication, but kept for compatibility.
> Real modern Intels can't send lowest priority IPIs and the chipset > directs external ones using processors' TPR.
False, new Intels most likely don't consider TPR. Please don't include this patch.
> AMD still has rough edges.
AMD behaves like its documentation states,
> + /* XXX: AMD (2:16.6.2 Lowest Priority Messages and Arbitration) > + * - uses the APR register (which also considers ISR and IRR), > + * - chooses the highest APIC ID when APRs are identical, > + * - and allows a focus processor.
but we don't differentiate. (It shouldn't create AMD-specific bugs.)
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