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    Subject[PATCH 3.14 19/77] powerpc/book3s: Fix partial invalidation of TLBs in MCE code.
    Date
    3.14-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>

    commit 682e77c861c4c60f79ffbeae5e1938ffed24a575 upstream.

    The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting
    in partial invalidation of TLBs which is not right. This patch fixes
    that by passing IS=0xc00 to invalidate whole TLB for successful recovery
    from TLB and ERAT errors.

    Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
    Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    arch/powerpc/kernel/mce_power.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/arch/powerpc/kernel/mce_power.c
    +++ b/arch/powerpc/kernel/mce_power.c
    @@ -78,7 +78,7 @@ static long mce_handle_derror(uint64_t d
    }
    if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
    if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
    - cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
    + cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
    /* reset error bits */
    dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
    }
    @@ -109,7 +109,7 @@ static long mce_handle_common_ierror(uin
    break;
    case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
    if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
    - cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
    + cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
    handled = 1;
    }
    break;



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