Messages in this thread | | | Date | Tue, 9 Sep 2014 09:37:21 -0500 | From | Aravind Gopalakrishnan <> | Subject | Re: [PATCH V3] edac, amd64_edac: Modify usage of amd64_read_dct_pci_cfg() |
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On 9/9/2014 6:42 AM, Borislav Petkov wrote: > On Tue, Sep 02, 2014 at 12:45:57PM -0500, Aravind Gopalakrishnan wrote: >> @@ -495,15 +493,56 @@ int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, >> u32 *val, const char *func); >> int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, >> u32 val, const char *func); >> - >> +void f15h_select_dct(struct amd64_pvt *pvt, u8 dct); >> #define amd64_read_pci_cfg(pdev, offset, val) \ >> __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) >> >> #define amd64_write_pci_cfg(pdev, offset, val) \ >> __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) >> >> -#define amd64_read_dct_pci_cfg(pvt, offset, val) \ >> - pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__) >> +/* >> + * Depending on the family, F2 DCT reads need special handling: >> + * >> + * K8: has a single DCT only and no address offsets >= 0x100 >> + * >> + * F10h: each DCT has its own set of regs >> + * DCT0 -> F2x040.. >> + * DCT1 -> F2x140.. >> + * >> + * F16h: has only 1 DCT >> + * >> + * For all above families, we should use the 'raw' version >> + * i.e, amd64_read_pci_cfg() function >> + */ >> +static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, >> + int offset, u32 *val) > Why is this function in the header since it is being used only in > amd64_edac.c, AFAICT? > > This makes you export f15h_select_dct() too, for no apparent reason. >
Hmm. Yeah, no particular reason. The earlier macro was here so I think I just expanded it as an inline function here.. I shall move it to amd64_edac.c and resend.
Thanks, -Aravind.
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