Messages in this thread | | | Date | Mon, 15 Sep 2014 12:09:10 -0300 | Subject | Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI | From | Fabio Estevam <> |
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On Mon, Sep 15, 2014 at 11:48 AM, Shawn Guo <shawn.guo@freescale.com> wrote:
> Shengjiu, > > Your analysis is right. I hope the following change will get the shared > gate clock code eventually does the right thing. > > Shawn > > diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c > index 84acdfd1d715..89abdf738dc9 100644 > --- a/arch/arm/mach-imx/clk-gate2.c > +++ b/arch/arm/mach-imx/clk-gate2.c > @@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) > struct clk_gate2 *gate = to_clk_gate2(hw); > > if (gate->share_count) > - return !!(*gate->share_count); > + return !!__clk_get_enable_count(hw->clk); > else > return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
This fixes the audio playback, thanks. Tested on a mx6qsabresd and also on mx6sx sdb:
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
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