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    Subject[PATCH v2 00/19] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages
    Date
    This patchset:
    1) provides several MMU TLB handling optimisation on MPC8xx.
    2) adds support of 16k pages on MPC8xx.
    All changes have been successfully tested on a custom board equipped with MPC885

    The two differences with first version of the patch are:
    1) I removed the patch number 10, which was implementing a 16 bit alignment of the
    PGDIR. It is not worth potentially wasting up to 64k of memory just for removing one
    instruction (ori).
    2) I managed to preserve r11 while calculating the level 2 address, therefore
    no more need to save r11 into CR.

    Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
    Tested-by: Christophe Leroy <christophe.leroy@c-s.fr>

    arch/powerpc/Kconfig | 2 +-
    arch/powerpc/include/asm/mmu-8xx.h | 2 +
    arch/powerpc/include/asm/pgtable-ppc32.h | 21 ++
    arch/powerpc/include/asm/pte-8xx.h | 7 +-
    arch/powerpc/include/asm/reg.h | 3 +-
    arch/powerpc/kernel/head_8xx.S | 342 +++++++++++-------------
    6 files changed, 187 insertions(+), 190 deletions(-)


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