Messages in this thread Patch in this message | | | From | Thierry Reding <> | Subject | [PATCH v3 5/6] PCI: tegra: Make sure the PCIe PLL is really reset | Date | Tue, 26 Aug 2014 17:11:37 +0200 |
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From: Eric Yuen <eyuen@nvidia.com>
Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset.
Signed-off-by: Eric Yuen <eyuen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/pci/host/pci-tegra.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 8264bce77750..0ce43764dd36 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -849,6 +849,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; pads_writel(pcie, value, soc->pads_pll_ctl); + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + usleep_range(20, 100); + /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM; -- 2.0.4
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