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    Subject[PATCH v2 4/6] PCI: tegra: Fix extended configuration space mapping
    Date
    From: Peter Daifuku <pdaifuku@nvidia.com>

    The 16 chunks of 64 KiB that need to be stitched together to make up the
    configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
    apart in physical address space. This is determined by the start of the
    extended register field (bits 24-27) in the physical mapping.

    Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
    Signed-off-by: Thierry Reding <treding@nvidia.com>
    ---
    drivers/pci/host/pci-tegra.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
    index bd53b123218b..8264bce77750 100644
    --- a/drivers/pci/host/pci-tegra.c
    +++ b/drivers/pci/host/pci-tegra.c
    @@ -383,7 +383,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
    for (i = 0; i < 16; i++) {
    unsigned long virt = (unsigned long)bus->area->addr +
    i * SZ_64K;
    - phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;
    + phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;

    err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
    if (err < 0) {
    --
    2.0.4


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