Messages in this thread | | | Date | Thu, 31 Jul 2014 17:47:47 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH 1/2] x86: AMD: mark TSC unstable on APU family 15h models 10h-1fh |
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On Thu, Jul 31, 2014 at 09:47:12AM +0000, Igor Mammedov wrote: > Due to erratum #778 from > "Revision Guide for AMD Family 15h Models 10h-1Fh Processors, > Publication # 48931, Issue Date: May 2013, Revision: 3.10" > > TSC on affected processor, a core may drift under certain conditions, > which makes initially synchronized TSCs to become unsynchronized.
Is this something you're seeing on a real system? If so, how do you trigger this?
Thanks.
-- Regards/Gruss, Boris.
Sent from a fat crate under my desk. Formatting is fine. --
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