lkml.org 
[lkml]   [2014]   [Jun]   [25]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH][v4] crypto: caam - Correct definition of registers in memory map
On Mon, Jun 23, 2014 at 03:08:28PM +0530, Ruchika Gupta wrote:
> Some registers like SECVID, CHAVID, CHA Revision Number,
> CTPR were defined as 64 bit resgisters. The IP provides
> a DWT bit(Double word Transpose) to transpose the two words when
> a double word register is accessed. However setting this bit
> would also affect the operation of job descriptors as well as
> other registers which are truly double word in nature.
> So, for the IP to work correctly on big-endian as well as
> little-endian SoC's, change is required to access all 32 bit
> registers as 32 bit quantities.
>
> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>

Patch applied.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt


\
 
 \ /
  Last update: 2014-06-25 17:41    [W:0.039 / U:1.184 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site