| Date | Wed, 9 Apr 2014 16:49:40 +0200 | From | Maxime Ripard <> | Subject | Re: [PATCH 05/15] clk: sunxi: add A31 APB0 clk gate defintions |
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On Wed, Apr 09, 2014 at 03:51:08PM +0200, Boris BREZILLON wrote: > Add APB0 gates support for the A31 SoC. > This gates are controlled by the PRCM (Power/Reset/Clock Management) block > and thus will act on a different iomem range. > > Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [unhandled content-type:application/pgp-signature] |