Messages in this thread | | | Date | Mon, 7 Apr 2014 17:26:20 +0300 | From | Peter De Schrijver <> | Subject | Re: [PATCH v2 1/3] clk: tegra: Fix PLLE programming |
| |
On Fri, Apr 04, 2014 at 03:55:13PM +0200, Thierry Reding wrote: > PLLE has M, N and P divider shift and width parameters that differ from > the defaults. Furthermore, when clearing the M, N and P divider fields > the corresponding masks were never shifted, thereby clearing only the > lowest bits of the register. This lead to a situation where the PLLE > programming would only work if the register hadn't been touched before. >
Will take this into tegra-clk-next. Mike, given that this is bug fix for a feature which is supposed to work, I think it's appropriate to try to get this into 3.15 still. I will make a pull-request on 3.15-rc1 as soon as it appears.
Cheers,
Peter.
| |