Messages in this thread | | | Date | Thu, 1 May 2014 00:10:58 +0200 (CEST) | From | Jiri Kosina <> | Subject | Re: 64bit x86: NMI nesting still buggy? |
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On Tue, 29 Apr 2014, H. Peter Anvin wrote:
> > [2] "A special case can occur if an SMI handler nests inside an NMI > > handler and then another NMI occurs. During NMI interrupt > > handling, NMI interrupts are disabled, so normally NMI interrupts > > are serviced and completed with an IRET instruction one at a > > time. When the processor enters SMM while executing an NMI > > handler, the processor saves the SMRAM state save map but does > > not save the attribute to keep NMI interrupts disabled. > > Potentially, an NMI could be latched (while in SMM or upon exit) > > and serviced upon exit of SMM even though the previous NMI > > handler has still not completed." > > I believe [2] only applies if there is an IRET executing inside the SMM > handler, which should not normally be the case. It might also have been > addressed since that was written, but I don't know.
Is there any chance that Intel would reveal what's behind this paragraph and how likely it is to expect such BIOSes in the wild?
Thanks,
-- Jiri Kosina SUSE Labs
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