Messages in this thread | | | Date | Tue, 01 Apr 2014 14:31:31 -0400 | From | Rik van Riel <> | Subject | Re: [PATCH] x86,mm: delay TLB flush after clearing accessed bit |
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On 04/01/2014 12:21 PM, Linus Torvalds wrote: > On Tue, Apr 1, 2014 at 9:11 AM, Rik van Riel <riel@redhat.com> wrote: >> >> Memory pressure is not necessarily caused by the same process >> whose accessed bit we just cleared. Memory pressure may not >> even be caused by any process's virtual memory at all, but it >> could be caused by the page cache. > > If we have that much memory pressure on the page cache without having > any memory pressure on the actual VM space, then the swap-out activity > will never be an issue anyway. > > IOW, I think all these scenarios are made-up. I'd much rather go for > simpler implementation, and make things more complex only in the > presence of numbers. Of which we have none.
We've been bitten by the lack of a properly tracked accessed bit before, but admittedly that was with the KVM code and EPT.
I'll add my Acked-by: to Shaohua's original patch then, and will keep my eyes open for any problems that may or may not materialize...
Shaohua?
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