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    Subject[PATCH 3.11 153/233] drm/radeon: set the full cache bit for fences on r7xx+
    Date
    3.11.10.4 -stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Alex Deucher <alexander.deucher@amd.com>

    commit d45b964a22cad962d3ede1eba8d24f5cee7b2a92 upstream.

    Needed to properly flush the read caches for fences.

    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
    ---
    drivers/gpu/drm/radeon/r600.c | 13 +++++++------
    drivers/gpu/drm/radeon/r600d.h | 1 +
    2 files changed, 8 insertions(+), 6 deletions(-)

    diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
    index c2d7eb6..30320a5 100644
    --- a/drivers/gpu/drm/radeon/r600.c
    +++ b/drivers/gpu/drm/radeon/r600.c
    @@ -2989,14 +2989,17 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
    struct radeon_fence *fence)
    {
    struct radeon_ring *ring = &rdev->ring[fence->ring];
    + u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
    + PACKET3_SH_ACTION_ENA;
    +
    + if (rdev->family >= CHIP_RV770)
    + cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;

    if (rdev->wb.use_event) {
    u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
    /* flush read cache over gart */
    radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
    - radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
    - PACKET3_VC_ACTION_ENA |
    - PACKET3_SH_ACTION_ENA);
    + radeon_ring_write(ring, cp_coher_cntl);
    radeon_ring_write(ring, 0xFFFFFFFF);
    radeon_ring_write(ring, 0);
    radeon_ring_write(ring, 10); /* poll interval */
    @@ -3010,9 +3013,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
    } else {
    /* flush read cache over gart */
    radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
    - radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
    - PACKET3_VC_ACTION_ENA |
    - PACKET3_SH_ACTION_ENA);
    + radeon_ring_write(ring, cp_coher_cntl);
    radeon_ring_write(ring, 0xFFFFFFFF);
    radeon_ring_write(ring, 0);
    radeon_ring_write(ring, 10); /* poll interval */
    diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
    index d079cb1..4dae42c 100644
    --- a/drivers/gpu/drm/radeon/r600d.h
    +++ b/drivers/gpu/drm/radeon/r600d.h
    @@ -1511,6 +1511,7 @@
    # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
    #define PACKET3_SURFACE_SYNC 0x43
    # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
    +# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
    # define PACKET3_TC_ACTION_ENA (1 << 23)
    # define PACKET3_VC_ACTION_ENA (1 << 24)
    # define PACKET3_CB_ACTION_ENA (1 << 25)
    --
    1.8.3.2


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