Messages in this thread | | | Date | Mon, 3 Feb 2014 09:33:49 +0100 | From | Alexandre Torgue <> | Subject | Re: [PATCH 1/4] ARM: STi: add stid127 soc support |
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On 01/31/2014 09:15 PM, Arnd Bergmann wrote: > On Friday 31 January 2014, srinivas kandagatla wrote: > >>> Sorry if I missed the initial review, but can you explain >>> why this is needed to start with? >> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set >> the way-size explicit here. > Unfortunately, we keep going back and forth on the L2 cache controller > setup between "it should work automatically" and "we don't want to > have configuration data in DT", where my personal opinion is that > the first one is more important here. > > Now, there are a couple of properties that are defined in > Documentation/devicetree/bindings/arm/l2cc.txt to let some of the > things get set up automatically already. Can you check which bits > are missing there, if any? Are they better described as "configuration" > or "hardware" settings? Hi Arnd,
Thanks for remarks. I will a have a look on it, but unfortunately not before 2 weeks.
Alex.
> > Arnd
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