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SubjectRe: [PATCH 5/5] arm64: add Crypto Extensions based synchronous core AES cipher
On Thu, Jan 30, 2014 at 07:20:38PM +0000, Ard Biesheuvel wrote:
> On 30 January 2014 19:56, Will Deacon <will.deacon@arm.com> wrote:
> > On Wed, Jan 29, 2014 at 04:50:46PM +0000, Ard Biesheuvel wrote:
> >> +static void aes_cipher_encrypt(struct crypto_tfm *tfm, u8 dst[], u8 const src[])
> >> +{
> >> + struct crypto_aes_ctx *ctx = crypto_tfm_ctx(tfm);
> >> + u32 rounds = 6 + ctx->key_length / 4;
> >
> > Can you document these constants please?
> >
>
> Sure.

Thanks.

> >> +
> >> + kernel_neon_begin();
> >> +
> >> + __asm__(" ld1 {v0.16b}, [%[in]] ;"
> >> + " ld1 {v1.16b}, [%[key]], #16 ;"
> >> + "0: aese v0.16b, v1.16b ;"
> >> + " subs %[rounds], %[rounds], #1 ;"
> >> + " ld1 {v1.16b}, [%[key]], #16 ;"
> >> + " beq 1f ;"
> >> + " aesmc v0.16b, v0.16b ;"
> >> + " b 0b ;"
> >> + "1: eor v0.16b, v0.16b, v1.16b ;"
> >> + " st1 {v0.16b}, [%[out]] ;"
> >> + : :
> >> + [out] "r"(dst),
> >> + [in] "r"(src),
> >> + [rounds] "r"(rounds),
> >> + [key] "r"(ctx->key_enc)
> >> + : "cc");
> >
> > You probably need a memory output to stop this being re-ordered by the
> > compiler. Can GCC not generate the addressing modes you need directly,
> > allowing you to avoid moving everything into registers?
> >
>
> Would a memory clobber work as well?

It would, but it could lead to suboptimal code generation by GCC (although
neon_{begin,end} may well stop GCC in its tracks anyway, so worth looking at
the disassembly).

> Re addressing modes: I would prefer to explicitly use v0 and v1, I
> have another patch pending that allows partial saves/restores of the
> NEON register file when called from interrupt context. I suppose I
> could use 'register asm("v0")' or something like that, but that won't
> make it any prettier.

It's not the use of v0/v1 that I was objecting to. I was hoping that we
could describe [in] and [out] as memory operands, so that GCC could
potentially reduce register usage for base + offset style addressing modes.
Unfortunately, I don't think we have such a constraint for AArch64 :(

If the disassembly looks ok, the "memory" clobber is probably our best bet.

Will


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