Messages in this thread | | | Date | Mon, 10 Feb 2014 17:36:06 +0100 | From | Fabrice Gasnier <> | Subject | Re: [RFC PATCH] ARM: Add imprecise abort enable/disable macro |
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On 02/10/2014 04:24 PM, Russell King - ARM Linux wrote: > On Mon, Feb 10, 2014 at 03:12:47PM +0000, Dave Martin wrote: >> Firstly, blindly adding 4 to PC is obviouly not right, partly because we >> might be running an unrelated thread by the time the abort fires, and >> also because the affected instruction might not be 4 bytes in size in a >> Thumb kernel. > Exactly. We ended up on some platforms having special accessors for PCI > where we included a number of 'mov r0, r0' instructions after the accessor > so we could properly cope with them - but this required knowledge that > we were going to only receive an imprecise abort from these accessors > and only for a few cycles after the instruction. > > However, that's not true with modern architectures. The point they're > received will _not_ be the load/store which resulted in the abort, and > in the case of a write, they could be many hundreds of cycles later, > especially if the write has been buffered. What about putting a memory barrier after a load/store ? CPU should wait for the operation to complete right ? > > So adding four to the PC is definitely a very /bad/ thing to do. >
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