Messages in this thread | | | From | Bean Huo 霍斌斌 (beanhuo) <> | Subject | RE: [V6 PATCH 1/1] driver:mtd:spi-nor: Add quad I/O support for Micron spi nor | Date | Mon, 8 Dec 2014 08:50:39 +0000 |
| |
>This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>For Micron SPI NOR flash,enabling or disabling quad I/O protocol can be done By two methods, which are to >use EVCR(Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command.There is no >difference between these two methods.Unfortunately,for some Micron spi nor flashes,there no ENTER Quad >I/O command(35h),such as n25q064.But for all current Micron spi nor,if it support quad I/O mode,using >EVCR definitely be supported.It is a recommended method to enable Quad I/O mode by EVCR,Quad I/O protocol >bit 7.When EVCR bit 7 is reset to 0,the SPI NOR flash will operate in quad I/O mode.
>This patch has been tested on N25Q512A and MT25TL256BAA1ESF.Micron spi nor of spi_nor_ids[] table all >support this method.
>Signed-off-by: bean huo <beanhuo@micron.com> >Acked-by: Marek Vasut <marex@denx.de> >--- >v1-v2: > Modified to that capture wait_till_ready() > return value,if error,directly return its > the value. >v2-v3: > Directly use the reurning error value of > read_reg and write_reg,instead of -EINVAL. > v3-v4: > Modify commit logs that wraped into 80 columns. > v4-v5: > Rebuild new patch based on latest linux-mtd. > v5-v6: > Rebuild patch based on latest l2-mtd. > add some comments. > Add SPI_NOR_QUAD_READ flag in the spi_nor_ids[] for Micron spi nor.
Hi,Brian
This patch is based on the latest l2-mtd,I don't know if can pass? I have one question is that about following code. I have added our Mciron quad flag into spi_nor_ids[] table,but line over 80 characters, If I divided one line into two lines,this will make spi_nor_ids[] table look ugly.I also find that There are other venders configure line that also over 80 characters,such as Spansion,Catalyst. So I don't divide my following configure line into two two lines,I don't know if this can Be accepted?
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
| |