Messages in this thread | | | From | "Liang, Kan" <> | Subject | RE: [PATCH 1/1] perf, x86: bug fix for cycles:p and cycles:pp on SLM | Date | Mon, 22 Dec 2014 13:34:33 +0000 |
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> > On Mon, Dec 08, 2014 at 06:27:43AM -0800, kan.liang@intel.com wrote: > > +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c > > @@ -568,8 +568,8 @@ struct event_constraint > > intel_atom_pebs_event_constraints[] = { }; > > > > struct event_constraint intel_slm_pebs_event_constraints[] = { > > - /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ > > - INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), > > + /* INST_RETIRED.ANY_P */ > > + INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), > > Should that not be: > INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), > > instead?
No, please refer to Table 19-20 in 19.10 Vol. 3 of SDM. PEBS is only supported with PMC0. There is no requirement to set inv and cmask.
Thanks, Kan
> > > /* Allow all events as PEBS with no flags */ > > INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), > > EVENT_CONSTRAINT_END > > -- > > 1.8.3.1 > >
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