Messages in this thread | | | Date | Fri, 7 Nov 2014 07:44:16 +0100 | From | Michal Simek <> | Subject | Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella |
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On 11/06/2014 06:22 PM, Andreas Färber wrote: > The Parallella board comes with a U-Boot bootloader that loads one of > two predefined FPGA bitstreams before booting the kernel. Both define an > AXI interface to the on-board Epiphany processor. > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > Cc: <stable@vger.kernel.org> # 3.17.x > Signed-off-by: Andreas Färber <afaerber@suse.de> > --- > Michal/Olof, please consider this trivial patch as a fix for 3.18.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Olof, Arnd: Can you please pick this directly?
Thanks, Michal
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