Messages in this thread | | | Date | Fri, 7 Nov 2014 10:31:34 -0800 | From | Scott Branden <> | Subject | Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround |
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On 14-11-05 09:01 PM, Stephen Warren wrote: > On 11/05/2014 12:00 AM, Scott Branden wrote: >> On 14-11-04 08:59 PM, Stephen Warren wrote: >>> On 10/30/2014 12:36 AM, Scott Branden wrote: >>>> Add a verify option to driver to print out an error message if a >>>> potential back to back write could cause a clock domain issue. >>> >>>> index f8c450a..11af27f 100644 >>> >>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND >>>> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); >>>> + struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv; >>>> + >>>> + if (bcm2835_host->previous_reg == reg) { >>>> + if ((reg != SDHCI_HOST_CONTROL) >>>> + && (reg != SDHCI_CLOCK_CONTROL)) { >>> >>> The comment in patch 3 says the problem doesn't apply to the data >>> register. Why does this check for these two registers rather than data? >> This Verify workaround patch still a work in progress. I'm still >> getting more info from the silicon designers on the back-to-back >> register writes that are affect. The spew of 0x20 or 0x28 or 0x2c >> register writes are all ok locations that don't need to be worked >> around. This patch needs to be corrected with the proper register rules >> still. Thanks for testing. Yes, I have work to do on the verify patch above still. > > FYI, I applied the series except for this patch, and everything > /appeared/ to work OK for a brief test (boot, log in, reboot). Still, > I'll hold off my Tested-by/acked-by until the comment in patch 3 and the > register list above match, and there's no log spew with everything applied. >
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