Messages in this thread | | | Date | Thu, 06 Nov 2014 22:02:34 +0100 | From | Barto <> | Subject | Re: [PATCH] PCI: Do not enable async suspend for JMicron chips |
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> The idea of a quirk is to work around a defect in a device. What is > the defect in this case? It seems there are two devices involved, > e.g. (from https://bugzilla.kernel.org/show_bug.cgi?id=81551): > > 02:00.0 JMicron Technology Corp. JMB363 SATA/IDE Controller > 02:00.1 JMicron Technology Corp. JMB363 SATA/IDE Controller >
in my case I don't have exactly the same lines in dmesg,
my JMicron JMB363/368 seems to have a different design, it's not exactly identical to JMB363 SATA/IDE Controller, in dmesg I can read this :
dmesg | grep micron
[ 0.860659] pata_jmicron 0000:03:00.1: enabling device (0000 -> 0001) [ 0.866760] scsi0 : pata_jmicron [ 0.870045] scsi1 : pata_jmicron
lspci :
lspci | grep JMicron
03:00.0 SATA controller: JMicron Technology Corp. JMB363 SATA/IDE Controller (rev 10) 03:00.1 IDE interface: JMicron Technology Corp. JMB368 IDE controller (rev 10)
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