Messages in this thread | | | Date | Fri, 31 Oct 2014 20:42:07 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH 01/17] x86: Make page cache mode a real type |
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On Fri, Oct 31, 2014 at 03:00:17PM +0100, Juergen Gross wrote: > At the moment there are a lot of places that handle setting or getting > the page cache mode by treating the pgprot bits equal to the cache mode. > This is only true because there are a lot of assumptions about the setup > of the PAT MSR. Otherwise the cache type needs to get translated into > pgprot bits and vice versa. > > This patch tries to prepare for that by introducing a separate type > for the cache mode and adding functions to translate between those and > pgprot values. > > To avoid too much performance penalty the translation between cache mode > and pgprot values is done via tables which contain the relevant > information. Write-back cache mode is hard-wired to be 0, all other > modes are configurable via those tables. For large pages there are > translation functions as the PAT bit is located at different positions > in the ptes of 4k and large pages. > > Signed-off-by: Stefan Bader <stefan.bader@canonical.com> > Signed-off-by: Juergen Gross <jgross@suse.com>
Just a clarification question: how is one to understand this attribution here? Is Stefan the original author, was he a reviewer, or? Because this SOB chain is misleading...
-- Regards/Gruss, Boris.
Sent from a fat crate under my desk. Formatting is fine. --
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