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    Subject[PATCH v4 13/20] usb: dwc3: set SUSPHY bit for all cores
    Date
    It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core
    initialization is completed above the dwc3 revision 1.94a.

    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Signed-off-by: Felipe Balbi <balbi@ti.com>
    ---
    drivers/usb/dwc3/core.c | 24 ++++++++++++++++++++++++
    1 file changed, 24 insertions(+)

    diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
    index 11b0ab08..e02c3b0 100644
    --- a/drivers/usb/dwc3/core.c
    +++ b/drivers/usb/dwc3/core.c
    @@ -374,6 +374,15 @@ static void dwc3_phy_setup(struct dwc3 *dwc)

    reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

    + /*
    + * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
    + * to '0' during coreConsultant configuration. So default value
    + * will be '0' when the core is reset. Application needs to set it
    + * to '1' after the core initialization is completed.
    + */
    + if (dwc->revision > DWC3_REVISION_194A)
    + reg |= DWC3_GUSB3PIPECTL_SUSPHY;
    +
    if (dwc->u2ss_inp3_quirk)
    reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;

    @@ -395,6 +404,21 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
    dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

    mdelay(100);
    +
    + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
    +
    + /*
    + * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
    + * '0' during coreConsultant configuration. So default value will
    + * be '0' when the core is reset. Application needs to set it to
    + * '1' after the core initialization is completed.
    + */
    + if (dwc->revision > DWC3_REVISION_194A)
    + reg |= DWC3_GUSB2PHYCFG_SUSPHY;
    +
    + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
    +
    + mdelay(100);
    }

    /**
    --
    1.9.1


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