| From | Greg Kroah-Hartman <> | Subject | [PATCH 3.16 051/357] i2c: rk3x: fix divisor calculation for SCL frequency | Date | Fri, 3 Oct 2014 14:27:17 -0700 |
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3.16-stable review patch. If anyone has any objections, please let me know.
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From: addy ke <addy.ke@rock-chips.com>
commit b4a7bd7a386dc6b0bb49cb47614e06e8295d495a upstream.
I2C_CLKDIV register descripted in the previous version of RK3x chip manual is incorrect. Plus 1 is required.
The correct formula: - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8 - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8 - (SCL Divsor) = 8 * ((CLKDIVL + 1) + (CLKDIVH + 1)) - SCL = PCLK / (CLK Divsor)
It will be updated to the latest version of chip manual.
Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--- drivers/i2c/busses/i2c-rk3x.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
--- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -433,12 +433,11 @@ static void rk3x_i2c_set_scl_rate(struct unsigned long i2c_rate = clk_get_rate(i2c->clk); unsigned int div; - /* SCL rate = (clk rate) / (8 * DIV) */ - div = DIV_ROUND_UP(i2c_rate, scl_rate * 8); - - /* The lower and upper half of the CLKDIV reg describe the length of - * SCL low & high periods. */ - div = DIV_ROUND_UP(div, 2); + /* set DIV = DIVH = DIVL + * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1)) + * = (clk rate) / (16 * (DIV + 1)) + */ + div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1; i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); }
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