Messages in this thread Patch in this message | | | From | Andrew Bresticker <> | Subject | [PATCH RESEND V4 1/9] of: Add NVIDIA Tegra XUSB mailbox binding | Date | Tue, 28 Oct 2014 15:27:48 -0700 |
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Add device-tree bindings for the Tegra XUSB mailbox which will be used for communication between the Tegra xHCI controller's firmware and the host processor.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> --- No changes from v3. Changes from v2: - Dropped channel specifier. - Added pointer to mailbox documentation. Changes from v1: - Updated to use common mailbox bindings. --- .../bindings/mailbox/nvidia,tegra124-xusb-mbox.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt new file mode 100644 index 0000000..b35ea6e --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra124-xusb-mbox.txt @@ -0,0 +1,32 @@ +NVIDIA Tegra XUSB mailbox +========================= + +The Tegra XUSB mailbox is used by the Tegra xHCI controller's firmware to +communicate requests to the host and PHY drivers. + +Refer to ./mailbox.txt for generic information about mailbox device-tree +bindings. + +Required properties: +-------------------- + - compatible: Should be "nvidia,tegra124-xusb-mbox". + - reg: Address and length of the XUSB FPCI registers. + - interrupts: XUSB mailbox interrupt. + - #mbox-cells: Should be 0. There is only one physical channel. + +Example: +-------- + xusb_mbox: mailbox@0,70098000 { + compatible = "nvidia,tegra124-xusb-mbox"; + reg = <0x0 0x70098000 0x0 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + + #mbox-cells = <0>; + }; + + usb@0,70090000 { + ... + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + ... + }; -- 2.1.0.rc2.206.gedb03e5
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