Messages in this thread Patch in this message | | | From | Graham Moore <> | Subject | [RFC 1/2] This is the documentation of the device tree bindings for the Cadence QSPI Flash Controller driver. | Date | Fri, 24 Oct 2014 13:34:20 -0500 |
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Signed-off-by: Graham Moore <grmoore@opensource.altera.com> --- .../devicetree/bindings/mtd/cadence_quadspi.txt | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cadence_quadspi.txt
diff --git a/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt new file mode 100644 index 0000000..0064fc3 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cadence_quadspi.txt @@ -0,0 +1,30 @@ +* Cadence Quad SPI controller + +Required properties: +- compatible : Should be "cdns,qspi-nor". +- reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. +- interrupts : Unit interrupt specifier for the controller interrupt. +- ext-decoder : Value of 0 means no external chipselect decoder is + connected, 1 means there is an external chipselect decoder connected. +- num-chipselect : Number of chip select lines. +- fifo-depth : Size of the data FIFO in words. +- bus-num : Number of the SPI bus to which the controller is connected. + +Example: + + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + ext-decoder = <0>; + num-chipselect = <4>; + fifo-depth = <128>; + bus-num = <2>; + } -- 1.7.9.5
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