Messages in this thread Patch in this message |  | | From | (Compostella, Jeremy) | Subject | [PATCH] x86: add the X86_FEATURE_NONSTOP_TSC_S3 cpu capability to new cpu | Date | Thu, 23 Oct 2014 19:27:26 +0200 |
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New Intel Atom processors (Baytrail and Cherryview), have a TSC that won't stop in S3 state, say the TSC value won't be reset to 0 after resume. This feature makes TSC a more reliable clocksource and could benefit the timekeeping code during system suspend/resume cycle.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> --- arch/x86/kernel/cpu/intel.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 1ef4562..8af195e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -92,11 +92,16 @@ static void early_init_intel(struct cpuinfo_x86 *c) set_sched_clock_stable(); } - /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ + /* + * Penwell, Cloverview, Valleyview and Cherryview have the TSC + * which doesn't sleep on S3. + */ if (c->x86 == 6) { switch (c->x86_model) { case 0x27: /* Penwell */ case 0x35: /* Cloverview */ + case 0x37: /* Valleyview */ + case 0x4C: /* Cherryview */ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); break; default: -- 1.9.1
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