Messages in this thread Patch in this message |  | | Date | Thu, 23 Oct 2014 12:51:23 +0200 | From | Peter Zijlstra <> | Subject | [PATCH 4/4] perf,x86: Introduce HSW cache numa events |
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Seeing how HSW-EP is now available and the SDM states the supplier and snoop info is identical to SNB/IVB, provide the cache numa events.
Cc: Andi Kleen <ak@linux.intel.com> Cc: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: http://lkml.kernel.org/n/tip-@git.kernel.org --- arch/x86/kernel/cpu/perf_event_intel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
--- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -563,6 +563,20 @@ static __initconst const u64 hsw_hw_cach [ C(RESULT_MISS) ] = HSW_DMND_PREFETCH|SNB_L3_MISS, }, }, + [ C(NODE) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = HSW_DMND_READ|SNB_DRAM_ANY, + [ C(RESULT_MISS) ] = HSW_DMND_READ|SNB_DRAM_REMOTE, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = HSW_DMND_WRITE|SNB_DRAM_ANY, + [ C(RESULT_MISS) ] = HSW_DMND_WRITE|SNB_DRAM_REMOTE, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = HSW_DMND_PREFETCH|SNB_DRAM_ANY, + [ C(RESULT_MISS) ] = HSW_DMND_PREFETCH|SNB_DRAM_REMOTE, + }, + }, }; static __initconst const u64 westmere_hw_cache_event_ids
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