Messages in this thread Patch in this message | | | From | Zhou Wang <> | Subject | [PATCH v1 2/2] ARM: dts: hip04: add GPIO pieces | Date | Wed, 22 Oct 2014 19:56:00 +0800 |
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Hisilicon Soc hip04 has four GPIO controllers, each one has 32 GPIOs and can be configured to be an interrupt controller.The GPIO controllers are compatible with the snps,dw-apb-gpio driver. This patch add the corresponding device tree nodes.
Signed-off-by: Zhou Wang <wangzhou.bry@gmail.com> --- arch/arm/boot/dts/hip04.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 93b6c90..c0f76b8 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -263,5 +263,80 @@ interrupts = <0 372 4>; }; + gpio@4003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4003000 0x1000>; + + gpio3: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 392 4>; + }; + }; + + gpio@4002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4002000 0x1000>; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 391 4>; + }; + }; + + gpio@4001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4001000 0x1000>; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 390 4>; + }; + }; + + gpio@4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4000000 0x1000>; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 389 4>; + }; + }; }; }; -- 1.7.9.5
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