Messages in this thread Patch in this message | | | From | Andi Kleen <> | Subject | [PATCH 3/8] x86: Add intrinsics/macros for new rd/wr fs/gs base instructions | Date | Tue, 14 Oct 2014 22:11:46 -0700 |
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From: Andi Kleen <ak@linux.intel.com>
Add C intrinsics and assembler macros for the new rd/wr fs/gs base instructions and for swapgs.
Very straight forward. Used in followon patch.
For assembler only a few standard registers used by entry_64.S are defined.
Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/include/asm/fsgs.h | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 arch/x86/include/asm/fsgs.h
diff --git a/arch/x86/include/asm/fsgs.h b/arch/x86/include/asm/fsgs.h new file mode 100644 index 0000000..1df5085 --- /dev/null +++ b/arch/x86/include/asm/fsgs.h @@ -0,0 +1,54 @@ +#ifndef _ASM_FSGS_H +#define _ASM_FSGS_H 1 + +#ifndef __ASSEMBLY__ + +static inline void swapgs(void) +{ + asm volatile("swapgs" ::: "memory"); +} + +/* Must be protected by X86_FEATURE_FSGSBASE check. */ + +static inline unsigned long rdgsbase(void) +{ + unsigned long gs; + asm volatile(".byte 0xf3,0x48,0x0f,0xae,0xc8 # rdgsbaseq %%rax" + : "=a" (gs) + :: "memory"); + return gs; +} + +static inline unsigned long rdfsbase(void) +{ + unsigned long fs; + asm volatile(".byte 0xf3,0x48,0x0f,0xae,0xc0 # rdfsbaseq %%rax" + : "=a" (fs) + :: "memory"); + return fs; +} + +static inline void wrgsbase(unsigned long gs) +{ + asm volatile(".byte 0xf3,0x48,0x0f,0xae,0xd8 # wrgsbaseq %%rax" + :: "a" (gs) + : "memory"); +} + +static inline void wrfsbase(unsigned long fs) +{ + asm volatile(".byte 0xf3,0x48,0x0f,0xae,0xd0 # wrfsbaseq %%rax" + :: "a" (fs) + : "memory"); +} + +#else + +/* Handle old assemblers. */ +#define RDGSBASE_R15 .byte 0xf3,0x49,0x0f,0xae,0xcf +#define WRGSBASE_RDI .byte 0xf3,0x48,0x0f,0xae,0xdf +#define WRGSBASE_R15 .byte 0xf3,0x49,0x0f,0xae,0xdf + +#endif /* __ASSEMBLY__ */ + +#endif -- 1.9.3
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