lkml.org 
[lkml]   [2014]   [Oct]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCHv3 2/3] gpio: sch: Add support for Intel Quark X1000 SoC
    Date
    Intel Quark X1000 provides a total of 16 GPIOs. The GPIOs are split between
    the legacy I/O bridge and the GPIO controller.

    GPIO-SCH is the GPIO pins on legacy bridge for Intel Quark SoC.
    Intel Quark X1000 has 2 GPIOs powered by the core power well and 6 from
    the suspend power well.

    This piece of work is derived from Dan O'Donovan's initial work for Quark
    X1000 enabling.

    Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
    ---
    drivers/gpio/Kconfig | 11 +++++++++--
    drivers/gpio/gpio-sch.c | 6 ++++++
    2 files changed, 15 insertions(+), 2 deletions(-)

    diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
    index 0959ca9..0e60f93 100644
    --- a/drivers/gpio/Kconfig
    +++ b/drivers/gpio/Kconfig
    @@ -371,25 +371,32 @@ config GPIO_VR41XX
    Say yes here to support the NEC VR4100 series General-purpose I/O Uint

    config GPIO_SCH
    - tristate "Intel SCH/TunnelCreek/Centerton GPIO"
    + tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"
    depends on PCI && X86
    select MFD_CORE
    select LPC_SCH
    help
    Say yes here to support GPIO interface on Intel Poulsbo SCH,
    - Intel Tunnel Creek processor or Intel Centerton processor.
    + Intel Tunnel Creek processor, Intel Centerton processor or
    + Intel Quark X1000 SoC.
    +
    The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
    powered by the core power rail and are turned off during sleep
    modes (S3 and higher). The remaining four GPIOs are powered by
    the Intel SCH suspend power supply. These GPIOs remain
    active during S3. The suspend powered GPIOs can be used to wake the
    system from the Suspend-to-RAM state.
    +
    The Intel Tunnel Creek processor has 5 GPIOs powered by the
    core power rail and 9 from suspend power supply.
    +
    The Intel Centerton processor has a total of 30 GPIO pins.
    Twenty-one are powered by the core power rail and 9 from the
    suspend power supply.

    + The Intel Quark X1000 SoC has 2 GPIOs powered by the core
    + power well and 6 from the suspend power well.
    +
    config GPIO_ICH
    tristate "Intel ICH GPIO"
    depends on PCI && X86
    diff --git a/drivers/gpio/gpio-sch.c b/drivers/gpio/gpio-sch.c
    index 6e89be9..952990f 100644
    --- a/drivers/gpio/gpio-sch.c
    +++ b/drivers/gpio/gpio-sch.c
    @@ -241,6 +241,12 @@ static int sch_gpio_probe(struct platform_device *pdev)
    sch->chip.ngpio = 30;
    break;

    + case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
    + sch->core_base = 0;
    + sch->resume_base = 2;
    + sch->chip.ngpio = 8;
    + break;
    +
    default:
    return -ENODEV;
    }
    --
    1.7.9.5


    \
     
     \ /
      Last update: 2014-10-16 06:01    [W:3.516 / U:0.008 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site