Messages in this thread Patch in this message |  | | From | Tomeu Vizoso <> | Subject | [PATCH 02/10] soc/tegra: Document long-ram-code property in nvidia,tegra20-apbmisc | Date | Fri, 10 Oct 2014 14:46:53 +0200 |
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Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..e2562ed 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,6 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: boolean that tells whether the ram code is long (4 bit) + or short (2 bit). If not present, false. -- 1.9.3
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