Messages in this thread | | | Date | Wed, 22 Jan 2014 09:26:22 -0500 | From | Sasha Levin <> | Subject | Re: [PATCH 13/15] sched: Use a static_key for sched_clock_stable |
| |
On 01/22/2014 08:14 AM, Markus Trippelsdorf wrote: > On 2014.01.22 at 13:30 +0100, Peter Zijlstra wrote: >> >On Wed, Jan 22, 2014 at 01:26:09PM +0100, Markus Trippelsdorf wrote: >>> > >On 2014.01.22 at 13:07 +0100, Peter Zijlstra wrote: >>>> > > >On Wed, Jan 22, 2014 at 01:00:48PM +0100, Markus Trippelsdorf wrote: >>>>> > > > >FYI it happens on real hardware on my machine: >>>>> > > > >... >>>>> > > > >[ 0.000000] Hierarchical RCU implementation. >>>>> > > > >[ 0.000000] NR_IRQS:4352 nr_irqs:712 16 >>>>> > > > >[ 0.000000] spurious 8259A interrupt: IRQ7. >>>>> > > > >[ 0.000000] Console: colour VGA+ 80x25 >>>>> > > > >[ 0.000000] console [tty0] enabled >>>>> > > > >[ 0.000000] hpet clockevent registered >>>>> > > > >[ 0.000000] tsc: Fast TSC calibration using PIT >>>>> > > > >[ 0.003333] tsc: Detected 3210.681 MHz processor >>>>> > > > >[ 60.375238] Calibrating delay loop (skipped), value calculated using timer frequency.. 6423.91 BogoMIPS (lpj=10702270) >>>>> > > > >[ 60.375240] pid_max: default: 32768 minimum: 301 >>>>> > > > >[ 60.375259] Mount-cache hash table entries: 256 >>>>> > > > >[ 60.375373] tseg: 0000000000 >>>>> > > > >[ 60.375377] CPU: Physical Processor ID: 0 >>>>> > > > >[ 60.375377] CPU: Processor Core ID: 0 >>>>> > > > >[ 60.375378] mce: CPU supports 6 MCE banks >>>>> > > > >[ 60.375382] LVT offset 0 assigned for vector 0xf9 >>>>> > > > >[ 60.375384] process: using AMD E400 aware idle routine >>>>> > > > >[ 60.375386] Last level iTLB entries: 4KB 512, 2MB 16, 4MB 8 >>>> > > > >>>> > > >Should have always happened like that I think. From the log it looks >>>> > > >like the moment we switch from jiffies to actual TSC in >>>> > > >arch/x86/kernel/tsc.c:sched_clock(). >>>> > > > >>>> > > >I don't think I changed the logic there, just switched from a condition >>>> > > >to a jump_label. >>> > > >>> > >Well, v3.13 was fine. So it's definitely a regression. But it may be >>> > >another issue. I will try to bisect later. >> > >> >OK, weird, I'll see if I can spot anything. > Unfortunately the issue is unbisectable (but the remaining commits are > all yours):
I've actually bisected it previously by fixing the build errors manually, and that took me to this patch you see in the subject line :)
Thanks, Sasha
| |