Messages in this thread Patch in this message | | | Date | Wed, 15 Jan 2014 17:38:40 -0800 | From | Stephen Boyd <> | Subject | Re: [PATCH v5 2/4] devicetree: bindings: Document Krait CPU/L1 EDAC |
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On 01/15, Stephen Boyd wrote: > > Ah sorry, I forgot to put the compatible property here like in > the dts change. I'll do that in the next revision. Yes we need a > compatible property here to match the platform driver. >
This is the replacement patch
-----8<------ From: Stephen Boyd <sboyd@codeaurora.org> Subject: [PATCH v9] devicetree: bindings: Document Krait CPU/L1 EDAC
The Krait CPU/L1 error reporting device is made up a per-CPU interrupt. While we're here, document the next-level-cache property that's used by the Krait EDAC driver.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Kumar Gala <galak@codeaurora.org> Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> --- Documentation/devicetree/bindings/arm/cpus.txt | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 91304353eea4..03a529e791c4 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -62,6 +62,20 @@ nodes to be present and contain the properties described below. Value type: <u32> Definition: must be set to 0 + - compatible + Usage: optional + Value type: <string> + Definition: should be one of the compatible strings listed + in the cpu node compatible property. This property + shall only be present if all the cpu nodes have the + same compatible property. + + - interrupts + Usage: required when node contains cpus with compatible + string "qcom,krait". + Value type: <prop-encoded-array> + Definition: L1/CPU error interrupt + - cpu node Description: Describes a CPU in an ARM based system @@ -191,6 +205,11 @@ nodes to be present and contain the properties described below. property identifying a 64-bit zero-initialised memory location. + - next-level-cache + Usage: optional + Value type: <phandle> + Definition: phandle pointing to the next level cache + Example 1 (dual-cluster big.LITTLE system 32-bit): cpus { @@ -382,3 +401,42 @@ cpus { cpu-release-addr = <0 0x20000000>; }; }; + + +Example 5 (Krait 32-bit system): + +cpus { + #address-cells = <1>; + #size-cells = <0>; + interrupts = <1 9 0xf04>; + compatible = "qcom,krait"; + + cpu@0 { + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + device_type = "cpu"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + device_type = "cpu"; + reg = <3>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + interrupts = <0 2 0x4>; + }; +}; -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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