lkml.org 
[lkml]   [2013]   [Sep]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 1/1] x86/iommu: correct ICS register offset
Hi Guys,
Though DMAR_ICS_REG is not used yet, I think this patch is
necessary. So please take a look at it.

Thanks
ZhenHua

On 09/13/2013 02:27 PM, Li, Zhen-Hua wrote:
> According to Intel Vt-D specs, the offset of Invalidation complete
> status register should be 0x9C, not 0x98.
>
> See Intel's VT-d spec, Revision 1.3, Chapter 10.4, Page 98;
>
> Signed-off-by: Li, Zhen-Hua <zhen-hual@hp.com>
> ---
> include/linux/intel-iommu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index 78e2ada..d380c5e 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -55,7 +55,7 @@
> #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
> #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
> #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
> -#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
> +#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
> #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
>
> #define OFFSET_STRIDE (9)
>



\
 
 \ /
  Last update: 2013-09-17 11:01    [W:0.137 / U:0.900 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site