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Subject[PATCH v2 4/4] BSC9131rdb/dts: Add nodes for supporting AIC
Date
From: Akhil Goyal <akhil.goyal@freescale.com>

BSC9131 is a hetrogenous system where Antenna interface controller
(AIC) is a part of DSP subsystem. But its configuration is done from
PA side. So a DSP node is added with appropriate CCSR address visible
to PA and hence the address space for AIC will be visible to PA.

BSC9131 support 3 AIC lanes for ADI interface and 3 for MAXIM type of
interface. This patch support only ADI lanes.

Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadhaya@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
---
arch/powerpc/boot/dts/bsc9131rdb.dts | 4 ++
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 38 +++++++++++++++++++++++++
2 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dts b/arch/powerpc/boot/dts/bsc9131rdb.dts
index e13d2d4..c134de7 100644
--- a/arch/powerpc/boot/dts/bsc9131rdb.dts
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dts
@@ -28,6 +28,10 @@
board_soc: soc: soc@ff700000 {
ranges = <0x0 0x0 0xff700000 0x100000>;
};
+
+ dsp_soc: sc3850@ff600000 {
+ ranges = <0x0 0x0 0xff600000 0x100000>;
+ };
};

/include/ "bsc9131rdb.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
index 5180d9d..487e949 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -191,3 +191,41 @@ global-utilities@e0000 {
fsl,has-rstcr;
};
};
+
+&dsp_soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ gcr@18000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,bsc9131-gcr", "fsl,bsc9132-gcr";
+ reg = <0x18000 0x200>;
+ };
+ aic@50000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,bsc9131-aic", "fsl,bsc9132-aic";
+ reg = <0x50000 0x200>;
+ interrupts = <49 2 0 0 53 2 0 0>;
+ lane0: aiclane@200 {
+ reg = <0x200 0x200>;
+ lane_id = <0>;
+ interrupts = <45 2 0 0>;
+ };
+
+ lane1: aiclane@400 {
+ reg = <0x400 0x200>;
+ lane_id = <1>;
+ interrupts = <46 2 0 0>;
+ };
+
+ lane2: aiclane@600 {
+ reg = <0x600 0x200>;
+ lane_id = <2>;
+ interrupts = <47 2 0 0>;
+ };
+ };
+};
+
+
--
1.6.3.1




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