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    SubjectRe: [PATCH v2 4/7] perf, x86: Save/resotre LBR stack during context switch
    On 07/04/2013 05:57 PM, Peter Zijlstra wrote:
    > On Mon, Jul 01, 2013 at 03:23:04PM +0800, Yan, Zheng wrote:
    >> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
    >> @@ -185,6 +185,13 @@ void intel_pmu_lbr_reset(void)
    >> intel_pmu_lbr_reset_32();
    >> else
    >> intel_pmu_lbr_reset_64();
    >> +
    >> + wrmsrl(x86_pmu.lbr_tos, 0);
    >> +}
    >
    > I double checked; my SDM Jun 2013, Vol 3C 35-93 very explicitly states that
    > MSR_LASTBRANCH_TOS is a read-only MSR. And afaicr all previous times I checked
    > this it did say this too.
    >

    thank you for point out this. I will update the patch

    Yan, Zheng


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